mirror of
https://github.com/Retropex/dolphin.git
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d485acdb51
Updated PTE.R bit on Write and Instruction fetch. Added code to read the PTE from MEM2 if the PTE is stored there. Refactored the two hash functions to reduce code duplication. Updated save state version.
313 lines
8.1 KiB
C++
313 lines
8.1 KiB
C++
// Copyright 2013 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#pragma once
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#include <tuple>
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#include "Common/BreakPoints.h"
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#include "Common/CommonTypes.h"
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#include "Core/Debugger/PPCDebugInterface.h"
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#include "Core/PowerPC/CPUCoreBase.h"
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#include "Core/PowerPC/Gekko.h"
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#include "Core/PowerPC/PPCCache.h"
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class PointerWrap;
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extern CPUCoreBase *cpu_core_base;
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namespace PowerPC
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{
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enum CoreMode
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{
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MODE_INTERPRETER,
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MODE_JIT,
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};
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// TLB cache
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#define TLB_SIZE 128
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#define TLB_WAYS 2
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#define NUM_TLBS 2
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#define HW_PAGE_INDEX_SHIFT 12
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#define HW_PAGE_INDEX_MASK 0x3f
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#define HW_PAGE_TAG_SHIFT 18
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#define TLB_FLAG_MOST_RECENT 0x01
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#define TLB_FLAG_INVALID 0x02
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struct tlb_entry
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{
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u32 tag;
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u32 paddr;
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u32 pte;
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u8 flags;
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};
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// This contains the entire state of the emulated PowerPC "Gekko" CPU.
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struct GC_ALIGNED64(PowerPCState)
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{
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u32 gpr[32]; // General purpose registers. r1 = stack pointer.
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u32 pc; // program counter
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u32 npc;
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// Optimized CR implementation. Instead of storing CR in its PowerPC format
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// (4 bit value, SO/EQ/LT/GT), we store instead a 64 bit value for each of
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// the 8 CR register parts. This 64 bit value follows this format:
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// - SO iff. bit 61 is set
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// - EQ iff. lower 32 bits == 0
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// - GT iff. (s64)cr_val > 0
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// - LT iff. bit 62 is set
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//
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// This has the interesting property that sign-extending the result of an
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// operation from 32 to 64 bits results in a 64 bit value that works as a
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// CR value. Checking each part of CR is also fast, as it is equivalent to
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// testing one bit or the low 32 bit part of a register. And CR can still
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// be manipulated bit by bit fairly easily.
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u64 cr_val[8];
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u32 msr; // machine specific register
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u32 fpscr; // floating point flags/status bits
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// Exception management.
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volatile u32 Exceptions;
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// Downcount for determining when we need to do timing
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// This isn't quite the right location for it, but it is here to accelerate the ARM JIT
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// This variable should be inside of the CoreTiming namespace if we wanted to be correct.
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int downcount;
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// XER, reformatted into byte fields for easier access.
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u8 xer_ca;
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u8 xer_so_ov; // format: (SO << 1) | OV
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// The Broadway CPU implements bits 16-23 of the XER register... even though it doesn't support lscbx
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u16 xer_stringctrl;
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#if _M_X86_64
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// This member exists for the purpose of an assertion in x86 JitBase.cpp
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// that its offset <= 0x100. To minimize code size on x86, we want as much
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// useful stuff in the one-byte offset range as possible - which is why ps
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// is sitting down here. It currently doesn't make a difference on other
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// supported architectures.
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std::tuple<> above_fits_in_first_0x100;
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#endif
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// The paired singles are strange : PS0 is stored in the full 64 bits of each FPR
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// but ps calculations are only done in 32-bit precision, and PS1 is only 32 bits.
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// Since we want to use SIMD, SSE2 is the only viable alternative - 2x double.
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GC_ALIGNED16(u64 ps[32][2]);
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u32 sr[16]; // Segment registers.
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// special purpose registers - controls quantizers, DMA, and lots of other misc extensions.
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// also for power management, but we don't care about that.
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u32 spr[1024];
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tlb_entry tlb[NUM_TLBS][TLB_SIZE / TLB_WAYS][TLB_WAYS];
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u32 pagetable_base;
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u32 pagetable_hashmask;
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InstructionCache iCache;
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};
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#if _M_X86_64
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static_assert(offsetof(PowerPC::PowerPCState, above_fits_in_first_0x100) <= 0x100, "top of PowerPCState too big");
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#endif
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enum CPUState
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{
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CPU_RUNNING = 0,
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CPU_STEPPING = 2,
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CPU_POWERDOWN = 3,
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};
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extern PowerPCState ppcState;
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extern Watches watches;
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extern BreakPoints breakpoints;
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extern MemChecks memchecks;
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extern PPCDebugInterface debug_interface;
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void Init(int cpu_core);
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void Shutdown();
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void DoState(PointerWrap &p);
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CoreMode GetMode();
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void SetMode(CoreMode _coreType);
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void SingleStep();
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void CheckExceptions();
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void CheckExternalExceptions();
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void CheckBreakPoints();
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void RunLoop();
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void Start();
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void Pause();
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void Stop();
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CPUState GetState();
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volatile CPUState *GetStatePtr(); // this oddity is here instead of an extern declaration to easily be able to find all direct accesses throughout the code.
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u32 CompactCR();
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void ExpandCR(u32 cr);
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void OnIdle(u32 _uThreadAddr);
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void OnIdleIL();
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void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst);
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// Easy register access macros.
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#define HID0 ((UReg_HID0&)PowerPC::ppcState.spr[SPR_HID0])
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#define HID2 ((UReg_HID2&)PowerPC::ppcState.spr[SPR_HID2])
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#define HID4 ((UReg_HID4&)PowerPC::ppcState.spr[SPR_HID4])
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#define DMAU (*(UReg_DMAU*)&PowerPC::ppcState.spr[SPR_DMAU])
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#define DMAL (*(UReg_DMAL*)&PowerPC::ppcState.spr[SPR_DMAL])
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#define MMCR0 ((UReg_MMCR0&)PowerPC::ppcState.spr[SPR_MMCR0])
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#define MMCR1 ((UReg_MMCR1&)PowerPC::ppcState.spr[SPR_MMCR1])
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#define PC PowerPC::ppcState.pc
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#define NPC PowerPC::ppcState.npc
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#define FPSCR ((UReg_FPSCR&)PowerPC::ppcState.fpscr)
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#define MSR PowerPC::ppcState.msr
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#define GPR(n) PowerPC::ppcState.gpr[n]
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#define rGPR PowerPC::ppcState.gpr
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#define rSPR(i) PowerPC::ppcState.spr[i]
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#define LR PowerPC::ppcState.spr[SPR_LR]
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#define CTR PowerPC::ppcState.spr[SPR_CTR]
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#define rDEC PowerPC::ppcState.spr[SPR_DEC]
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#define SRR0 PowerPC::ppcState.spr[SPR_SRR0]
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#define SRR1 PowerPC::ppcState.spr[SPR_SRR1]
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#define SPRG0 PowerPC::ppcState.spr[SPR_SPRG0]
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#define SPRG1 PowerPC::ppcState.spr[SPR_SPRG1]
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#define SPRG2 PowerPC::ppcState.spr[SPR_SPRG2]
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#define SPRG3 PowerPC::ppcState.spr[SPR_SPRG3]
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#define GQR(x) PowerPC::ppcState.spr[SPR_GQR0+x]
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#define TL PowerPC::ppcState.spr[SPR_TL]
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#define TU PowerPC::ppcState.spr[SPR_TU]
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#define rPS0(i) (*(double*)(&PowerPC::ppcState.ps[i][0]))
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#define rPS1(i) (*(double*)(&PowerPC::ppcState.ps[i][1]))
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#define riPS0(i) (*(u64*)(&PowerPC::ppcState.ps[i][0]))
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#define riPS1(i) (*(u64*)(&PowerPC::ppcState.ps[i][1]))
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} // namespace
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enum CRBits
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{
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CR_SO = 1,
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CR_EQ = 2,
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CR_GT = 4,
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CR_LT = 8,
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CR_SO_BIT = 0,
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CR_EQ_BIT = 1,
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CR_GT_BIT = 2,
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CR_LT_BIT = 3,
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};
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// Convert between PPC and internal representation of CR.
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inline u64 PPCCRToInternal(u8 value)
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{
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u64 cr_val = 0x100000000;
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cr_val |= (u64)!!(value & CR_SO) << 61;
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cr_val |= (u64)!(value & CR_EQ);
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cr_val |= (u64)!(value & CR_GT) << 63;
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cr_val |= (u64)!!(value & CR_LT) << 62;
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return cr_val;
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}
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// convert flags into 64-bit CR values with a lookup table
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extern const u64 m_crTable[16];
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// Warning: these CR operations are fairly slow since they need to convert from
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// PowerPC format (4 bit) to our internal 64 bit format. See the definition of
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// ppcState.cr_val for more explanations.
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inline void SetCRField(int cr_field, int value)
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{
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PowerPC::ppcState.cr_val[cr_field] = m_crTable[value];
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}
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inline u32 GetCRField(int cr_field)
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{
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u64 cr_val = PowerPC::ppcState.cr_val[cr_field];
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u32 ppc_cr = 0;
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// SO
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ppc_cr |= !!(cr_val & (1ull << 61));
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// EQ
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ppc_cr |= ((cr_val & 0xFFFFFFFF) == 0) << 1;
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// GT
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ppc_cr |= ((s64)cr_val > 0) << 2;
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// LT
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ppc_cr |= !!(cr_val & (1ull << 62)) << 3;
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return ppc_cr;
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}
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inline u32 GetCRBit(int bit)
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{
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return (GetCRField(bit >> 2) >> (3 - (bit & 3))) & 1;
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}
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inline void SetCRBit(int bit, int value)
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{
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if (value & 1)
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SetCRField(bit >> 2, GetCRField(bit >> 2) | (0x8 >> (bit & 3)));
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else
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SetCRField(bit >> 2, GetCRField(bit >> 2) & ~(0x8 >> (bit & 3)));
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}
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// SetCR and GetCR are fairly slow. Should be avoided if possible.
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inline void SetCR(u32 new_cr)
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{
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PowerPC::ExpandCR(new_cr);
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}
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inline u32 GetCR()
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{
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return PowerPC::CompactCR();
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}
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inline void SetCarry(int ca)
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{
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PowerPC::ppcState.xer_ca = ca;
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}
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inline int GetCarry()
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{
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return PowerPC::ppcState.xer_ca;
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}
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inline UReg_XER GetXER()
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{
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u32 xer = 0;
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xer |= PowerPC::ppcState.xer_stringctrl;
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xer |= PowerPC::ppcState.xer_ca << XER_CA_SHIFT;
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xer |= PowerPC::ppcState.xer_so_ov << XER_OV_SHIFT;
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return xer;
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}
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inline void SetXER(UReg_XER new_xer)
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{
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PowerPC::ppcState.xer_stringctrl = new_xer.BYTE_COUNT + (new_xer.BYTE_CMP << 8);
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PowerPC::ppcState.xer_ca = new_xer.CA;
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PowerPC::ppcState.xer_so_ov = (new_xer.SO << 1) + new_xer.OV;
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}
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inline int GetXER_SO()
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{
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return PowerPC::ppcState.xer_so_ov >> 1;
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}
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inline void SetXER_SO(int value)
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{
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PowerPC::ppcState.xer_so_ov |= value << 1;
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}
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void UpdateFPRF(double dvalue);
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